This invention relates to a computer aided design (CAD) for designing integrated circuits such as large-scale integrated circuits (LSIs) or logic circuits and, more particularly, to a fault simulation method for checking whether or not any fault can be detected in a designed integrated circuit.
As known in the art, a "fault simulation" is to check whether or not any fault can be detected in the designed integrated circuit by generating a test pattern for checking whether or not the designed integrated circuit satisfies a predetermined performance and/or a predetermined function and by carrying out simulation, using the generated test pattern, behavior of the designed integrated circuit including faults. In other words, although a test program is used to verify validity in a completed LSI or logic circuit, the "fault simulation" is used to check a fault coverage for all of faults in a checked object by the test program and to confirm validity of the test program.
In prior art, the fault simulation carries out first a good simulation on the integrated circuit having no fault and subsequently carries out simulations on the integrated circuit having each fault. As a result, the fault simulation takes a very long processing time in comparison with a logic simulation.
Now, models of several levels are used as an unit of the simulation. That is, there are a model of switch level (which will be referred to as a "switch model"), a model of gate level (which will be called a "gate model"), and a model of function level (which will be referred to as a "function model"). The "switch model" is a most primitive model and deals with a transfer gate or the like in a metal oxide semiconductor (MOS) circuit. In addition, the "gate model" deals with basic gates such as an AND gate, an OR gate and so on. Furthermore, the "function model" deals with a higher model than the gate model. The function model is referred to as a superior model. The superior model has an operation speed which is faster than that of the gate model. In other words, the superior model is operable at a higher speed than that of the gate model.
A conventional fault simulation method is published in Japanese Unexamined Patent Publication of Tokkai No. Sho 64-46,846 or JP-A 64-46,846 (which will be herein called a reference) on Feb. 21, 1989 which is hereby incorporated herein by reference. The fault simulation method according to JP-A 64-46,846 comprises the steps of dividing an entire circuit into a plurality of partial circuits, of representing the partial circuits by superior models operable at a high speed except for a particular one thereof, and of carrying out simulation of faults. That is, the conventional fault simulation method uses the gate model operable at a low speed as the particular partial circuit where any fault is assumed or defined to perform operation on the particular partial circuit. Such a fault simulation is called a hierarchical fault simulation. In the hierarchical fault simulation, it is possible to perform propagation of the fault by representing the particular partial circuit by the gate model and by representing remaining partial circuits where the fault propagates by the superior models.
More specifically, in the hierarchical fault simulation, each partial circuit is preliminarily represented by both of the gate model and the superior model and switching operation is made so as to select, as the particular partial circuit, the partial circuit represented by the gate model and to select, as the remaining partial circuits, the partial circuits represented by the superior models. As described above, on simulation, the hierarchical fault simulation deals with a circuit arrangement where the particular partial circuit represented by the gate model and the remaining partial circuits represented by the higher superior models are mixed. In addition, the superior model may be, for example, C-like description.
At any rate, the hierarchical fault simulation method carries out simulation with the particular partial circuit represented by the gate model and the remaining partial circuits represented by the superior models mixed. As described above, inasmuch as the particular partial circuit where the fault is assumed is represented by the gate model in the conventional fault simulation method, the conventional fault simulation is disadvantageous in that it is impossible to operate the particular partial circuit at the high speed.